DVB-T2 Decoder IP
Description
Ubiso DVB-T2 IP is a highly optimized DVB-T2 Decoder solution designed by Ubiso for next generation terrestrial digital television reception.
Ubiso DVB-T2 IP converts demodulated I/Q signals into a bit stream for use by the video decoder. This includes all de-interleaving, FEC decoding and output processing.
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Product Brief

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Key Features
- All DVB-T2 modes
- Dedicated DVB-T2 Pre-Processing with Resource Sharing
- Processing one data and one common PLP concurrently
- Frequency Deinterleaving
- Time-, Cell-, Parity- and Bit Deinterleaving
- QAM Demultiplexing
- L1-Pre and L1-Post Processing
- Zig-zag deinterleaving
- Depadding and Depuncturing
- L1 inband signalling
- I/Q mapping to LLR values
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- Optimized high performance FEC engine
- Single LDPC/BCH Decoder shared for all modes
- FEC engine parameters optimized for target throughput / application
- DVB-T2 L1 Decoding
- Output Processing
- TS / GSE / GFPS / GCS output
- De-Jitter Buffering and PLP Re-combination into single output stream
- Standard AHB Interfaces for Host control and Memory Access
- Optimized compile options targeted for ASIC and FPGA applications
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Ubiso DVB-T2 IP in a DVB-T2 receiver (either iDTV or set-top box) application:

Block Diagram of DVB-T2 IP:

Contact us for more information
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