DVB-S2 - Decoder

The UBISO Dual DVB-S2 FEC IP is a low-cost, highly optimized dual DVB-S2 IP targeted for best performance at the smallest area. The preprocessing blocks (mapping I/Q values to LLR values, deinterleaver) and the postprocessing blocks (BCH decoder, BBHEADER extraction,..) are customized to the LDPC decoder architecture. This allows the data to get in and out to the LDPC decoder as quickly as possible, thus exploiting the full capacity of our high performance LDPC decoder. The enhanced LDPC Decoder uses a modified Gauss-Seidel-Aglrotihm resulting in a very low gate count and optimal frequency and therefore making the IP extremely competitive.

We published our DVB-S/S2 IP in the international technical conference
"Design, Automation and Test in Europe"(DATE) 2009, see...

Block Diagram

Functionality

• Receiving I and Q values of two independent channels
• Mapping I and Q values to Log-Likelihood-Ratio (LLR) values (demodulate)
• Deinterleaving
• Decoding each LDPC codeword using iterative soft decision decoding
  (Turbo Decoding Message Passing Algorithm)
• Decoding each BCH codeword
• Descrambling frame (BB scrambling)
• Capturing BB Header and depacketizing
• Computing the CRC check

Features

• Architecture reworked in order to reduce layout effort
• New architecture (lower complexity, lower power):
  
  • Applying Gauss-Seidel (Turbo-Decoding, Layered) principle on all possible parity check nodes.
    (Calculating double permutations without any latency)
  • Computing 90 check nodes in parallel, instead of 360 (reduced hardware)
• Log-Likelihood-Ratio (LLR) compression algorithm reduces edge memory requirements
• Decoding of optional code rates
• Power saving via different dynamic decoding stop criteria
  
  • if decoding is completed (xH=0)
  • if codeword is undecodable (examining the SNR via calculating the variable node reliability)
• BCH decoder reworked in order to match new LDPC decoder architecture

LDPC improvements

...in throughput and convergence

The Ubiso LDPC Decoder uses a modified Gauss-Seidel Algorithm, capable of calculating any permutations in one clock cycle, even submatrices containing two or more permutations. This increases the throughput and convergence by factor two compared to conventional decoding algorithms. These facts allows us to split the size of the submatrizes from 360 to any  required  factor. Hence reducing gate count and relaxing the routing congestions.

=> reduced level of parallelism from 360 to 90 check processing units (CPU)s
=> significant gate count reduction
=> significantly easier to route

...in memory requirements

Ubisos LLR compression algorithm reduces the required memory size. The compression as well as the decompression process is completely pipelined,  no additional latency time is added. A conventional decoder requires a memory of 1.7 MBits in order to store the extrinsic values, our enhanced compressing algorithms needs only 0.97 MBit!